Production Data
WM8805
RIGHT JUSTIFIED MODE
In Right Justified Mode, the LSB of DIN is sampled by the WM8805 on the rising edge of BCLK
preceding an LRCLK transition. The LSB of the output data (DOUT) changes on the falling edge of
BCLK preceding an LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLK
is high during the left samples and low during the right samples (Figure 19).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DIN / DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 19 Right Justified Mode
I2S MODE
In I2S Mode, the MSB of DIN is sampled by the WM8805 on the second rising edge of BCLK
following an LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK
following an LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLK is low
during the left samples and high during the right samples (Figure 20).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
1 BCLK
1 BCLK
DIN / DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 20 I2S Mode
PD Rev 4.1 September 07
47
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
