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WM8805 参数 Datasheet PDF下载

WM8805图片预览
型号: WM8805
PDF下载: 下载PDF文件 查看货源
内容描述: 8 : 1数字接口收发器PLL [8:1 Digital Interface Transceiver with PLL]
分类和应用:
文件页数/大小: 65 页 / 848 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8805  
Production Data  
AUDIO DATA FORMATS  
Five interface formats are supported:  
Left Justified Mode  
Right Justified Mode  
I2S Mode  
DSP Mode A  
DSP Mode B  
The MSB is sent first in all formats. Word lengths of 16, 20 and 24 bits are supported.  
Audio data for each stereo channel is clocked with the BCLK signal. Data is time multiplexed with the  
LRCLK, indicating whether the left or right channel data is present. The LRCLK is also used as a  
timing reference to indicate the beginning or end of the data words.  
In Left Justified, Right Justified and I2S modes the minimum number of BCLKs per LRCLK period is  
two times the number of bits in the selected word length. LRCLK must be high for a minimum of n  
BCLKs and low for a minimum of n BCLKs, where n is the number of bits in an audio word. Any mark  
to space ratio on LRCLK is acceptable provided the above requirements are met.  
The data may also be output in DSP Mode A or Mode B, with LRCLK used as a frame sync to  
identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is two times the  
number of bits in the word length.  
LEFT JUSTIFIED MODE  
In Left Justified mode, the MSB of DIN is sampled by the WM8805 on the first rising edge of BCLK  
following an LRCLK transition. The MSB of the output data (DOUT) changes on the same falling  
edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. LRCLK is high  
during the left samples and low during the right samples (Figure 18).  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCLK  
BCLK  
DIN / DOUT  
1
2
3
n
n-2 n-1  
1
2
3
n
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 18 Left Justified Mode  
PD Rev 4.1 September 07  
46  
w
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