Product Preview
WM8802
READ REGISTER OUTPUT CONTENTS
REGISTER ADDRESS
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
CCB address: 0xEB
FSDAT7
FSDAT6
FSDAT5
FSDAT4
FSDAT3
FSDAT2
FSDAT1
FSDAT0
FSDAT [7:0]
fs counter data output
•
•
FSDAT [7:0] is the fs calculation counter value. The data length is 8 bits, FSDAT0 is LSB and
FSDAT7 is MSB.
The relation between the count value and fs is expressed by the following equation.
fs = 6144/FSDAT (kHz)
•
•
fs calculation is performed using a 6.144MHz clock so the calculation accuracy is determined
by this clock.
The calculation counter value is 8 bit output so the fs that can be calculated is higher than
24kHz.
READ REGISTER 3 (FIRST 48 CHANNEL STATUS BITS)
•
The first 48 channel status bits can be read with the demodulation function.
•
The read channel status data is a LSB output.
•
For read, CCB address is set to 0xEC.
•
The channel status data cannot be updated after the CCB address is set.
•
The relation between the read registers and the channel status data is shown below.
REGISTER
DO0
BIT NO.
CONTENTS
Application
REGISTER
DO24
DO25
DO26
DO27
DO28
DO29
DO30
DO31
DO32
DO33
DO34
DO35
DO36
DO37
DO38
DO39
DO40
DO41
DO42
DO43
DO44
DO45
DO46
DO47
BIT NO.
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
Bit 32
Bit 33
Bit 34
Bit 35
Bit 36
Bit 37
Bit 38
Bit 39
Bit 40
Bit 41
Bit 42
Bit 43
Bit 44
Bit 45
Bit 46
Bit 47
CONTENTS
Bit 0
Bit 1
Sampling frequency
DO1
Control
DO2
Bit 2
DO3
Bit 3
DO4
Bit 4
Clock accuracy
Not defined
DO5
Bit 5
DO6
Bit 6
Not defined
DO7
Bit 7
DO8
Bit 8
Category code
Word length
DO9
Bit 9
DO10
DO11
DO12
DO13
DO14
DO15
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Not defined
Source number
Channel number
PP Rev 1.1 April 2004
59
w