Product Preview
WM8774
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
DOUT
DIN
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
DOUT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN setup time to BCLCK
rising edge
10
10
DIN hold time from BCLK
rising edge
Table 2 Digital Audio Data Timing – Master Mode
PP Rev 1.0 June 2002
9
ꢀꢀ