Production Data
WM8776
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
ADC/DACMCLK System clock
pulse width high
tMCLKH
tMCLKL
tMCLKY
11
11
28
ns
ns
ns
ADC/DACMCLK System clock
pulse width low
ADC/DACMCLK System clock
cycle time
1000
ADC/DACMCLK Duty cycle
Power-saving mode activated
Normal mode resumed
40:60
2
60:40
10
After MCLK stopped
After MCLK re-started
µs
MCLK
cycle
0.5
1
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed
in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a
write to the volume update register bit is required to restore the correct volume settings.
PD Rev 4.0 April 2005
w
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
