Production Data
WM8776
DIGITAL AUDIO INTERFACE – SLAVE MODE
DACBCLK
ADCBCLK
ADCLRC
DVD
Controller
WM8776
CODEC
DACLRC
DOUT
DIN
Figure 4 Audio Interface – Slave Mode
tBCH
tBCL
ADCBCLK/
DACBCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DIN
tDD
tDH
DOUT
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADC/DACBCLK cycle time
tBCY
tBCH
50
20
ns
ns
ADC/DACBCLK pulse width
high
ADC/DACBCLK pulse width
low
tBCL
20
10
ns
ns
DACLRC/ADCLRC set-up
time to ADC/DACBCLK
rising edge
tLRSU
DACLRC/ADCLRC hold
time from ADC/DACBCLK
rising edge
tLRH
10
ns
DIN set-up time to
DACBCLK rising edge
tDS
tDH
tDD
10
10
0
ns
ns
ns
DIN hold time from
DACBCLK rising edge
DOUT propagation delay
10
from ADCBCLK falling edge
Table 3 Digital Audio Data Timing – Slave Mode
Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8776 interface is tolerant of phase
variations or jitter on these signals.
PD Rev 4.0 April 2005
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
