WM8776
Production Data
3-WIRE MPU INTERFACE TIMING
tCSL
tCSH
CE
tSCY
tCSS
tSCS
tSCH
tSCL
CL
DI
LSB
tDSU
tDHO
Figure 6 SPI Compatible (3-wire) Control Interface Input Timing (MODE=1)
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
CL rising edge to CE rising edge
CL pulse cycle time
SYMBOL
tSCS
MIN
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
tSCY
ns
CL pulse width low
tSCL
ns
CL pulse width high
tSCH
ns
DI to CL set-up time
CL to DI hold time
tDSU
ns
tDHO
tCSL
ns
CE pulse width low
ns
CE pulse width high
tCSH
ns
CE rising to CL rising
tCSS
ns
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
PD Rev 4.0 April 2005
12
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
