Production Data
WM8776
ADC INPUT MIXER AND POWERDOWN CONTROL
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R21 (15h)
0010101
4:0
AMX[4:0]
00001
ADC left channel input mixer
control bits (see Table 16)
ADC Input Mux
R13 (0Dh)
0001101
6
AINPD
0
Input mux and buffer powerdown
0: Input mux and buffer
enabled
Powerdown Control
1: Input mux and buffer
powered down
Register bits AMX[4:0] control the left and right channel inputs into the stereo ADC. The default is
AIN1. One bit of AMX is allocated to each stereo input pair to allow the signals to be mixed before
being digitised by the ADC. For example, if AMX[4:0] is 00101, the input signal to the ADC will be
(AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel.
However if the analogue input buffer is powered down, by setting AINPD, then all 5-channel mixer
inputs are switched to buffered VMIDADC.
AMX[4:0]
LEFT ADC INPUT
RIGHT ADC INPUT
00001
00010
00100
01000
10000
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN1R
AIN2R
AIN3R
AIN4R
AIN5R
Table 16 ADC Input Mixer
AIN1L/R
AMX[0]
AIN2L/R
AMX[1]
AIN3L/R
AMX[2]
AIN4L/R
AMX[3]
AIN5L/R
AMX[4]
Figure 25 ADC Input Mixer
PD Rev 4.0 April 2005
39
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
