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WM8775
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversample rate to 64fs.
REGISTER ADDRESS
R12(0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
ADC oversampling rate select
0: 128x oversampling
3
ADCOSR
0
0001100
ADC Oversampling Rate
1: 64x oversampling
POWERDOWN MODE AND ADC DISABLE
Setting the PDWN register bit immediately powers down the WM8775, including the references,
overriding all other powerdown control bits. All trace of the previous input samples is removed, but all
control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised.
It is recommended that the 4-channel input mux and buffer, and ADC are powered down before
setting PDWN.
The ADC may also be powered down by setting the ADCPD disable bit. Setting ADCPD will disable
the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when
ADCPD is reset.
REGISTER ADDRESS
R13(0Dh)
BIT
LABEL
DEFAULT
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
0
PDWN
0
0001101
Powerdown Control
1: Power Down Mode
ADC Disable:
1
6
ADCPD
AINPD
0
0
0 : Normal Mode
1: Power Down Mode
Analogue Input Disable:
0 : Normal Mode
1 : Power Down Mode
ADC GAIN CONTROL
The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the
analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right.
The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows
further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 11 shows how the
register maps the analogue and digital gains.
LAG/RAG[7:0]
ATTENUATION
LEVEL
ANALOGUE PGA
DIGITAL
ATTENTUATION
00(hex)
01(hex)
:
-∞ dB (mute)
-103dB
-21dB
-21dB
:
Digital mute
-82dB
:
:
-21.5dB
-21dB
:
A4(hex)
A5(hex)
:
-21dB
-21dB
:
-0.5dB
0dB
:
CF(hex)
:
0dB
0dB
0dB
:
:
:
FE(hex)
FF(hex)
+23.5dB
+24dB
+23.5dB
+24dB
0dB
0dB
Table 11 Analogue and Digital Gain Mapping for ADC
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes. The ADC volume and mute also applies to the bypass signal path.
PP Rev 1.8, June 2004
21
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
