WM8775
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In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a
write, the gain will update only when the input signal approaches zero (midrail). This minimises
audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which
will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
3
TOD
0
Analogue PGA Zero cross detect
timeout disable
0000111
0 : Timeout enabled
1: Timeout disabled
Timeout Clock Disable
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R14(0Eh)
0001110
Attenuation
ADCL
7:0
LAG[7:0]
ZCLA
11001111
(0dB)
Attenuation data for Left channel ADC gain in 0.5dB steps. See
Table 11.
8
0
Left channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
R15(0Fh)
0001111
7:0
8
RAG[7:0]
ZCRA
11001111
(0dB)
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 11.
Attenuation
ADCR
0
0
0
0
Right channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
R21(15h)
0010101
8
7
6
LRBOTH
MUTELA
MUTERA
Right channel input PGA controlled by left channel register
0 : Right channel uses RAG.
1 : Right channel uses LAG.
Mute for left channel ADC
0: Normal Operation
ADC Input Mux
R21(15h)
0010101
ADC Mute
1: Mute ADC left
Mute for right channel ADC
0: Normal operation
1: Mute ADC right
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
R11(0Bh)
BIT
LABEL
DEFAULT
DESCRIPTION
ADC High pass filter disable:
0: High pass filter enabled
1: High pass filter disabled
8
ADCHPD
0
0001011
ADC Control
PP Rev 1.8, June 2004
22
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
