WM8775
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DSP LATE MODE
The MSB of the left channel ADC data is output on DOUT and changes on the same falling
edge of BCLK as the low to high ADCLRC transition and may be sampled on the rising edge
of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 16).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
n
1
2
n
1
n-1
n-1
DOUT
MSB
LSB
Input Word Length (IWL)
Figure 16 DSP Late Mode Timing Diagram – ADC Data Output
CONTROL INTERFACE OPERATION
The WM8775 is controlled using a 3-wire serial interface in a SPI compatible configuration or
a 2-wire serial interface mode. The interface type is selected by the MODE pin as shown in
Table 9.
MODE
Control Mode
2 wire interface
3 wire interface
0
1
Table 9 Control Interface Selection via MODE pin
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI as
well as MODE may have an input high level of 5V while DVDD is 3V. Input thresholds are determined
by DVDD.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the
program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in
Figure 17.
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 17 3-Wire SPI Compatible Interface
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CE is edge sensitive – the data is latched on the rising edge of CE.
PP Rev 1.8, June 2004
18
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
