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WM8775
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 13 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of
BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is
low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1 BCLK
1 BCLK
1
2
3
n
1
2
3
n
DOUT
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 14 I2S Mode Timing Diagram
DSP EARLY MODE
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.
The right channel ADC data is contiguous with the left channel data (Figure 15)
1 BCLK
1 BCLK
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Word Length (WL)
Figure 15 DSP Early Mode Timing Diagram – ADC Data Output
PP Rev 1.8, June 2004
17
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
