Production Data
WM8772EFT – 32 LEAD TQFP
WM8722EFT - 32 LEAD TQFP
MASTER CLOCK TIMING
tMCLKL
ADCMCLK/
DACMCLK
tMCLKH
tMCLKY
Figure 37 ADC and DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
ADCMCLK and DACMCLK
System clock pulse width high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
ADCMCLK and DACMCLK
System clock pulse width low
ADCMCLK and DACMCLK
System clock cycle time
28
ADCMCLK and DACMCLK Duty
cycle
40:60
60:40
Table 13 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
ADCBCLK
ADCLRC
DACBCLK
DSP/
WM8772
CODEC
ENCODER/
DECODER
DACLRC
DOUT
DIN1/2/3
3
Figure 38 Audio Interface - Master Mode
PD Rev 4.2 October 2005
43
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
