WM8772EFT – 32 LEAD TQFP
Production Data
ADCBCLK/
DACBCLK
(Outputs)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
DOUT
DIN1/2/3
tDST
tDHT
Figure 39 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
ADCBCLK/DACBCLK
falling edge
tDL
0
10
ns
DOUT propagation delay
from ADCBCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN1/2/3 setup time to
DACBCLK rising edge
10
10
DIN1/2/3 hold time from
DACBCLK rising edge
Table 14 Digital Audio Data Timing – Master Mode
PD Rev 4.2 October 2005
44
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
