Production Data
WM8772EDS – 28 LEAD SSOP
To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a
transistor clamp circuit arrangement may be added to the output connectors of the system. A
recommended clamp circuit configuration is shown below.
Figure 36 Output Clamp Circuit
When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until
capacitor C49 is fully charged. With transistor Q10 held ‘on’, NPN transistors Q4 to Q9 of the clamp
circuits are also switched on holding the system outputs near to GND. When capacitor C49 is fully
charged transistors Q10 and Q4 to Q9 are switched off setting the outputs active.
When the +VS power supply is removed, PNP transistor Q11 of the trigger circuit is switched on. In
turn, transistors Q4 to Q9 of the clamp circuits are switched on holding the outputs of the evaluation
board near to GND until the rest of the circuitry on the board has settled.
Note: It is recommended that low Vcesat switching transistors should be used in this circuit to ensure
that the clamp is applied before the rest of the circuitry has time to power down.
Important: If a trigger circuit such as the one shown is to be used, it is important that the +VS
supply drops quicker than any other supply to ensure that the outputs are clamped during the
period when ‘pop’ noise may occur.
PD Rev 4.2 October 2005
41
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
