Production Data
WM8772EDS – 28 LEAD SSOP
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of
BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of BCLK preceding a LRC transition and may be sampled on the rising edge of BCLK.
LRC are high during the left samples and low during the right samples (Figure 24).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 24 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the second rising edge of
BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of BCLK following an LRC transition and may be sampled on the rising edge of
BCLK. LRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
1 BCLK
1 BCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 25 I2S Mode Timing Diagram
PD Rev 4.2 October 2005
25
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
