WM8771
Product Preview
ADCLRC/DACLRC Polarity or DSP Early/Late mode select
2
3
LRP
BCP
0
0
Left Justified / Right Justified /
I2S
DSP Mode
0: Data in-line with
ADCLRC/DACLRC
0: Standard DACLRC Polarity
1: Inverted DACLRC Polarity
BITCLK Polarity
1: Data delayed by 1 BCLK
0: Normal - DIN[3:0], DACLRC & ADCLRC sampled on
rising edge of BCLK; DOUT changes on falling edge of
BCLK.
1: Inverted - DIN[3:0], DACLRC & ADCLRC sampled on
falling edge of BCLK; DOUT changes on rising edge of
BCLK.
5:4
WL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
8
ADCHPD
0
ADC Highpass Filter Disable:
0: Highpass Filter enabled
1: Highpass Filter disabled
10111
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC ratio select:
Master Mode
control
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
3
ADCOSR
0
ADC oversample rate select
0: 128x oversampling
1: 64x oversapmling
6:4
DACRATE[2:0]
010
Master Mode MCLK:DACLRC ratio select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
8
0
MS
0
0
Maser/Slave interface mode select
0: Slave Mode – ADCLRC, DACLRC and BCLK are inputs
1: Master Mode – ADCLRC, DACLRC and BCLK are outputs
11000
PWDN
Chip Powerdown Control (works in tandem with ADCD and
DACD):
Powerdown
Control
1
ADCD
1
ADC powerdown:
5:2
DACD[3:0]
1111
DAC powerdown
11001
4:0
5
LAG[4:0]
MUTE
01100
0
Attenuation data for left channel ADC gain in 1dB steps
Attenuation
ADCL
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
0
Setting LRBOTH will write the same gain value to LAG[4:0 and
RAG[4:0]
PP Rev 2.0 December 2001
36
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
