WM8771
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DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
ADCLRC
DSP
WM8771
CODEC
ENCODER/
DECODER
DACLRC
DOUT
DIN1/2/3/4
4
Figure 4 Audio Interface – Slave Mode
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DIN1/2/3/4
DOUT
tDD
tDH
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tLRSU
DACLRC/ADCLRC hold
time from BCLK rising edge
tLRH
tDS
tDH
tDD
10
10
10
0
ns
ns
ns
ns
DIN1/2/3/4 set-up time to
BCLK rising edge
DIN1/2/3/4 hold time from
BCLK rising edge
DOUT propagation delay
from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8771 interface is tolerant of phase variations or jitter on these signals.
PP Rev 2.0 December 2001
10
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
