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WM8771
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
DSP/
WM8771
CODEC
ENCODER/
DECODER
DACLRC
DOUT
DIN1/2/3/4
4
Figure 2 Audio Interface - Master Mode
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
DOUT
DIN1/2/3/4
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
DOUT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN1/2/3/4 setup time to
BCLCK rising edge
10
10
DIN1/2/3/4 hold time from
BCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
PP Rev 2.0 December 2001
9
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
