Production Data
WM8770
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
28
1000
60:40
10
40:60
2
Power-saving mode activated
Normal mode resumed
After MCLK stopped
After MCLK re-started
µs
0.5
1
MCLK
cycle
Table 1 Master Clock Timing Requirements
Note: If MCLK period is longer than maximum specified above, DACs are powered down with internal digital audio filters
being reset. In this mode, all registers will retain their values and can be accessed in the normal manner through the
control interface. Once MCLK is restored, the DACs are automatically powered up.
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
DSP/
WM8770
CODEC
ENCODER/
DECODER
DACLRC
DOUT
DIN1/2/3/4
4
Figure 2 Audio Interface - Master Mode
PD Rev 4.1 June 2005
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
