WM8770
Production Data
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
DOUT
DIN1/2/3/4
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
DOUT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DIN1/2/3/4 setup time to
BCLCK rising edge
10
10
DIN1/2/3/4 hold time from
BCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
PD Rev 4.1 June 2005
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
