Production Data
WM8770
tRCES tRCLH
RESETB
CE
tCP tCS
tCH
tSCY
tSCL
tSCH
CL
DI
A7
D15
tDSU
tDHO
Figure 7 3 Wire CCB Compatible Interface Input Timing Information – CL Stopped Low
tRCES tRCLH
RESETB
tCH
tCP tCS
CE
tSCY
tSCL
tSCH
CL
DI
A7
D15
tDSU
tDHO
Figure 8 3 Wire CCB Compatible Interface Input Timing Information – CL Stopped High
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless
otherwise stated.
PARAMETER
CE to RESETB setup time
RESETB to CL hold time
DI to CL setup time
SYMBOL
tRCES
tRCLH
tDSU
MIN
20
20
20
20
20
20
20
TYP
MAX
UNIT
ns
ns
ns
CL to DI hold time
tDHO
ns
CL to CE setup time
CE to CL wait time
tCS
ns
tCP
ns
CL to CE hold time
ns
t
CH
CL pulse width high
CL pulse width low
CL pulse cycle time
tSCH
tSCL
tSCY
30
30
80
ns
ns
ns
Table 5 3 wire CCB Compatible Interface Input Timing Information
PD Rev 4.1 June 2005
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
