WM8770
Production Data
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3/4 is sampled by the WM8770 on the first rising edge of
BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on
the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK.
ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 14).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DIN1/2/3/4/
DOUT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 14 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8770 on the rising edge of BCLK
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of BCLK preceding a ADCLRC transition and may be sampled on the rising edge of
BCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples
(Figure 15).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DIN1/2/3/4/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 15 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8770 on the second rising edge of BCLK
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of
BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
1 BCLK
1 BCLK
DIN1/2/3/4/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 16 I2S Mode Timing Diagram
PD Rev 4.1 June 2005
22
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
