Production Data
WM8770
Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and MCLK
frequencies.
SAMPLING
RATE
System Clock Frequency (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
(DACLRC/
ADCLRC)
DACRATE
=000
DACRATE
=001
ADCRATE/
DACRATE
=010
ADCRATE/
DACRATE
=011
ADCRATE/
DACRATE
=100
ADCRATE/
DACRATE
=101
32kHz
44.1kHz
48kHz
4.096
5.6448
6.144
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
9.216
96kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
192kHz
Unavailable Unavailable Unavailable Unavailable
Table 8 Master Mode ADC/DACLRC Frequency Selection
BCLK is also generated by the WM8770. The frequency of BCLK depends on the mode of operation.
In 128/192fs modes (DACRATE=000 or 001) BCLK
= MCLK/2. In 256/384/512fs modes
(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as
the audio interface mode then BCLK=MCLK. This is to ensure that there are sufficient BCLKs to
clock in all eight channels. Note that DSP mode cannot be used in 128fs mode for word lengths
greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
ZERO DETECT
The WM8770 has a zero detect circuit for each DAC channel which detects when 1024 consecutive
zero samples have been input. Two zero flag outputs (ZFLAG1 and ZFLAG2) may be programmed to
output the zero detect signals (see Table 9) which may then be used to control external muting
circuits. A ‘1’ on ZFLAG1 or ZFLAG2 indicates a zero detect. When a DAC is powered down
ZFLAG1 and ZFLAG2 will go high by default if the Zero Detect is selected for that DAC. When this
DAC is powered off, the Bypass path is selected and there is an external mute circuit controlled by
ZFLAG1 or ZFLAG2, the Zero Detect feature should be de-selected or the output will be muted.
The zero detect may also be used to automatically enable the PGA mute by setting IZD. The zero
flag output may be disabled by setting DZFM to 0000. The zero flag signal for a DAC channel will
only be enabled if that channel is enabled as an input to the output summing stage.
DZFM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZFLAG1
ZFLAG2
Zero flag disabled
All channels zero
Left channels zero
Channel 1 zero
Channel 1 zero
Channel 1 zero
Channel 1 zero
Channel 2 zero
Channel 2 zero
Channel 3 zero
Channels 1-3 zero
Channel 1 zero
Channel 1 left zero
Channel 2 left zero
Channel 3 left zero
Channel 4 left zero
Zero flag disabled
All channels zero
Right channels zero
Channels 2-4 zero
Channel 2 zero
Channel 3 zero
Channel 4 zero
Channel 3 zero
Channel 4 zero
Channel 4 zero
Channel 4 zero
Channels 2 & 3 zero
Channel 1 right zero
Channel 2 right zero
Channel 3 right zero
Channel 4 right zero
Table 9 Zero Flag Output Select
PD Rev 4.1 June 2005
19
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
