WM8753L
Advanced Information
REGISTER
ADDRESS
BIT
LABEL
BCLKINV
DEFAULT
DESCRIPTION
R4 (04h)
7
6
5
4
0
Hi-Fi DAC BCLK invert bit (for master
and slave modes)
0 = BCLK not inverted
1 = BCLK inverted
Digital
Hi-Fi
Audio
Interface
Format
MS
0
0
0
Hi-Fi Interface Master / Slave Mode
Control
1 = Enable Master Mode
0 = Enable Slave Mode
LRSWAP
LRP
Hi-Fi DAC Left/Right channel swap
1 = swap left and right DAC data in
audio interface
0 = output left and right data as normal
Hi-Fi DAC right, left and I2S modes –
LRC polarity
1 = invert LRC polarity
0 = normal LRC polarity
Hi-Fi DAC DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
1:0
WL[1:0]
10
10
Hi-Fi DAC Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
FORMAT[1:0]
Hi-Fi DAC Audio Data Format Select
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Right justified
Table 53 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
REGISTER
ADDRESS
BIT
8:6
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
Digital Audio
Interface
PBMODE [2:0] 000
Voice Interface Master mode VXCLK
rate select
000 : VXCLK = MCLK
Control
001 : VXCLK = MCLK / 2
010 : VXCLK = MCLK / 4
011 : VXCLK = MCLK / 8
100 : VXCLK = MCLK / 16
5:3
BMODE [2:0]
000
HiFi Interface Master mode BCLK rate
select
000 : BCLK = MCLK
001 : BCLK = MCLK / 2
010 : BCLK = MCLK / 4
011 : BCLK = MCLK / 8
100 : BCLK = MCLK / 16
Table 54 BCLK and VXCLK Master Mode Rate Select
AI Rev 3.1 June 2004
59
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
