Advanced Information
WM8753L
PMS selects Voice audio interface operation in master or slave mode. In Master mode VXCLK and
VXFS are outputs. The frequency of FS is set by the sample rate control bits SRMODE and PSR. In
Slave mode VXCLK and VXFS are inputs.
REGISTER
ADDRESS
BIT
LABEL
ADCDOP
DEFAULT
DESCRIPTION
R3 (03h)
Digital Voice
Audio
Interface
Format
8
0
ADC data output to ADCDAT and
VXDOUT enable
0 = ADC data output to ADCDAT or
VXDOUT as selected by IFMODE[1:0]
1 = ADC data output to ADCDAT and
VXDOUT
7
6
VXCLKINV
PMS
0
0
VXCLK invert bit (for master and slave
modes)
0 = VXCLK not inverted
1 = VXCLK inverted
Voice Interface Master / Slave Mode
Control
1 = Enable Master Mode
0 = Enable Slave Mode
5
4
MONO
PLRP
0
0
Mono ADC data only
1 = output left channel ADC data only
0 = output left and right ADC data
Vx DAC and ADC right, left and I2S
modes VXCLK polarity
1 = invert VXCLK polarity
0 = normal VXCLK polarity
Vx DAC and ADC DSP Mode – mode
A/B select
1 = MSB is available on 1st VXCLK rising
edge after VXFS rising edge (mode B)
0 = MSB is available on 2nd VXCLK
rising edge after VXFS rising edge
(mode A)
3:2
1:0
PWL[1:0]
10
10
Vx DAC and ADC Audio Data Word
Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
PFORMAT[1:
0]
Vx DAC and ADC Audio Data Format
Select
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Right justified
Table 55 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
AI Rev 3.1 June 2004
60
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
