Advanced Information
WM8753L
Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor.
This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and
L/ROUT1, L/ROUT2 and MONO1 can be controlled using the VROI bit in register 27. The default is
low (500Ω), so that any capacitors on the outputs can charge up quickly at start-up. If a high
impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to
about 90kΩ.
REGISTER
ADDRESS
BIT
LABEL
VROI
DEFAULT
DESCRIPTION
R45 (2Dh)
3
0
VREF to analogue output resistance
Additional (1)
0: 500 Ω
1: 90 kΩ
Table 43 Disabled Outputs to VREF Resistance
HEADPHONE SWITCH
Pin 43 (GPIO4) can be used as a headphone switch control input to automatically disable the speaker
output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this
mode, enabled by setting HPSWEN, pin 43 switches between headphone and speaker outputs (e.g.
when pin 43 is connected to a mechanical switch in the headphone socket to detect plug-in). The
HPSWPOL bit reverses the polarity of pin 43. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits
in register 22 must also be set for headphone and speaker output (see Table 44 and Table 45). The
GPIO4 pin has an internal pull-up/pull-down which can be enabled by setting register bits
GPIO4M[1:0]. For cap-less headphone connections a pull-down should be used if VMID is greater
than GPIO4 VIH, otherwise a pull-up should be used. GPIO4 can also be used to generate an
interrupt. See GPIO and Interrupt Controller Section. The GPIO4 input has a debounce circuit to
remove glitches on the input caused by a jack insert in order to prevent the outputs being powered on
and off. This debounce circuit is clocked from a slow clock with period = 221 x input clock. The input
clock can be selected to be either mclk or pcmclk using SLWCLK.
HPSWEN HPSWPOL
GPIO4
L/ROUT1 L/ROUT2 Headphone
Speaker
enabled
no
(pin 43)
(reg. 22)
(reg. 22)
enabled
no
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
1
1
0
0
0
0
1
1
X
X
0
1
X
X
0
1
0
1
0
1
0
1
X
X
0
1
X
X
no
yes
no
yes
yes
no
yes
no
no
yes
no
no
yes
no
no
no
no
yes
no
no
yes
no
Table 44 Headphone Switch Operation
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Headphone Switch Enable
0 : Headphone switch disabled
1 : Headphone switch enabled
R45 (2Dh)
Output
Control
6
5
0
HPSWEN
0
HPSWPOL
SLWCLK
0
0
Headphone Switch Polarity
0 : GPIO4 high = headphone
1 : GPIO4 high = speaker
R52 (34h)
Timeout and Headphone switch clock
source
Clock Control
0 = mclk
1 = pcm clk
Table 45 Headphone Switch
AI Rev 3.1 June 2004
46
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
