Production Data
WM8750JL
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8750JL, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.
However, since setting DIGENB has no effect on the power consumption of other system components
external to the WM8750JL, it is preferable to disable the master clock at its source wherever possible.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
0
DIGENB
0
Master clock disable
Additional Control
(1)
0: master clock enabled
1: master clock disabled
Table 44 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set
to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may
prevent DACs and ADCs from re-starting correctly.
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in
a slight decrease in noise performance but will also reduce the power consumption of the device. In
USB mode ADCOSR must be set to 0, i.e. 128x oversampling.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
1
0
ADCOSR
0
0
ADC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
Additional Control
(2)
DACOSR
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
Table 45 ADC and DAC Oversampling Rate Selection
ADCOSR set to ‘1’, 64x oversample mode, is not supported in USB mode (USB=1).
SAVING POWER AT HIGHER SUPPLY VOLTAGES
The analogue supplies to the WM8750JL can run from 1.8V to 3.6V. By default, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down
to 1.8V. At lower voltages, performance can be improved by increasing the bias current. If low power
operation is preferred the bias current can be left at the default setting. This is controlled as shown
below.
REGISTER
ADDRESS
BIT
LABEL DEFAULT
DESCRIPTION
R23 (17h)
7:6
VSEL
[1:0]
11
Analogue Bias optimization
Additional
Control(1)
00: Highest bias current, optimized for AVDD=1.8V
01: Bias current optimized for AVDD=2.5V
1X: Lowest bias current, optimized for AVDD=3.3V
PD, April 2012, Rev 4.1
49
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
