Production Data
WM8750JL
REGISTER
ADDRESS
BIT
6:5
LABEL
ADCPOL
DEFAULT
00
DESCRIPTION
R5 (05h)
00 = Polarity not inverted
01 = L polarity invert
ADC and DAC
Control
[1:0]
10 = R polarity invert
11 = L and R polarity invert
4
0
HPOR
0
0
Store dc offset when high-pass
filter disabled
1 = store offset
0 = clear offset
ADCHPD
ADC high-pass filter enable
(Digital)
HPFLREN = 0
1 = Disable high-pass filter on left
and right channels
0 = Enable high-pass filter on left
and right channels
HPFLREN = 1
0 = High-pass enabled on left,
disabled on right
1 = High-pass enabled on right,
disabled on left
R27 (1Bh)
5
HPFLREN
0
ADC high-pass filter left or right
enable
0 = High-pass filter enable/disable
on left and right channels
controlled by ADCHPD
1 = High-pass filter enabled on left
or right channel, as selected by
ADCHPD
Table 10 ADC Signal Path Control
HPFLREN
ADCHPD
HIGH PASS MODE
High-pass filter enabled on left and right
channels
0
0
1
0
1
High-pass filter disabled on left and right
channels
0
1
1
High-pass filter enabled on left channel,
disabled on right channel
High-pass filter disabled on left channel,
enabled on right channel
Table 11 ADC High Pass Filter Enable Modes
PD, April 2012, Rev 4.1
21
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
