Production Data
WM8750JL
INTERNAL POWER ON RESET CIRCUIT
DCVDD
AVDD
VDD
T1
Power on Reset
Internal PORB
Circuit
GND
DGND
Figure 6 Internal Power on Reset Circuit Schematic
The WM8750JL includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to
reset the digital logic into a default state after power up. The power on reset circuit is powered from
DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a
minimum threshold.
Figure 7 Typical Power-Up Sequence
Figure 7 shows a typical power-up sequence. When DCVDD and AVDD rise above the minimum
thresholds, Vpord_dcvdd and Vpord_avdd, there is enough voltage for the circuit to guarantee the
Power on Reset is asserted low and the chip is held in reset. In this condition, all writes to the control
interface are ignored. When DCVDD rises to Vpor_dcvdd_on and AVDD rises to Vpor_avdd_on,
PORB is released high and all registers are in their default state and writes to the control interface
may take place. If DCVDD and AVDD rise at different rates then PORB will only be released when
DCVDD and AVDD have both exceeded the Vpor_dcvdd_on and Vpor_avdd_on thresholds.
On power down, PORB is asserted low whenever DCVDD drops below the minimum threshold
Vpor_dcvdd_off or AVDD drops below the minimum threshold Vpor_avdd_off.
SYMBOL
Vpord_dcvdd
MIN
0.4
0.9
0.5
0.4
TYP
0.6
MAX
0.8
UNIT
V
V
V
V
Vpor_dcvdd_on
Vpor_avdd_on
Vpor_avdd_off
1.26
0.7
1.6
0.9
0.6
0.8
Table 2 Typical POR Operation (typical values, not tested)
PD, April 2012, Rev 4.1
15
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
