WM8750JL
Production Data
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Bit Clock Timing Information
BCLK rise time (10pF load)
tBCLKR
tBCLKF
tBCLKDS
tBCLKDS
3
3
ns
ns
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK = MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
50:50
TMCLKDS
tDL
10
40
ns
ns
ns
ns
tDDA
tDST
tDHT
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DACDAT
ADCDAT
tDD
tDH
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
ADCLRC/DACLRC set-up time to BCLK rising edge
ADCLRC/DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
tDD
10
Note:
BCLK period should always be greater than or equal to MCLK period.
PD, April 2012, Rev 4.1
12
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
