WM8750JL
Production Data
CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
1.3
600
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
300
300
Setup Time (Stop Condition)
Data Hold Time
600
0
900
5
Pulse width of spikes that will be suppressed
PD, April 2012, Rev 4.1
14
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
