Production Data
WM8737L
REGISTER
ADDRESS
BIT
LABEL
LMZC
DEFAULT
DESCRIPTION
R2 (02h)
Audio Path Left
None (first
gain
change
would
Left Mic preamp Zero-Cross Enable
0: Change gain immediately
3
1: Change gain on zero crossing only
overwrite!)
LPZC
1
Left PGA Zero-Cross Enable
0: Change gain immediately
1: Change gain on zero crossing only
Left Zero-Cross Time-Out
00: 256/fs
2
LZCTO[1:0]
11
1:0
01: 512/fs
10: 1024/fs
11: 2048/fs (42.67ms at 48kHz)
This timeout applies to both the PGA
and mic preamp zero-cross watchdog
timers.
R3 (03h)
RMZC
None
1
Right Mic preamp Zero-Cross Enable
Same as LMZC but for right channel
Right PGA Zero-Cross Enable
3
Audio Path
Right
2
RPZC
Same as LMZC but for right channel
Right Zero-Cross Time-Out
RZCTO[1:0]
11
1:0
Same as LMZC but for right channel
Table 8 Zero-Cross Detection Control
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8737L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit
feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC
full-scale input level is proportional to AVDD. With a 3.3V supply voltage the full scale level is 1.0 Volt
rms (+/-1.414 Volts peak). Any voltage greater than full-scale will overload the ADC and cause
distortion.
ADC THD+N VERSUS POWER CONTROL
The ADCs can be operated in ‘normal mode’, which offers best THD+N performance at the cost of
highest power dissipation, or in ‘low power mode’ which offers significant power savings at the cost of
slightly reduced THD+N performance. The ADCs operating mode is controlled by the LP bit in register
R5. USB mode is not compatible with low power mode, so the LP bit must be set to 0 if USB mode is
selected.
See the ‘Power Consumption’ section for power requirements in both modes.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADC Control
LP
0
ADC power mode control
2
0: Both ADCs in normal mode (best
THD+N)
1: Both ADCs in low power mode
Table 9 ADC Power Control
ADC DIGITAL FILTER
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated below.
PD, Rev 4.4, January 2012
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
