WM8728
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MPU 3-WIRE INTERFACE TIMING
CSBIWL
LATI2S
tCSSU
tCSSH
tCSL
tCSH
tSCY
tCSS
tSCS
tSCH
tSCL
SCKDSD
SDIDEM
LSB
tDSU
tDHO
Figure 5 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCKDSD rising edge to LATI2S
rising edge
tSCS
40
ns
SCKDSD pulse cycle time
SCKDSD pulse width low
SCKDSD pulse width high
tSCY
tSCL
tSCH
tDSU
80
20
20
20
ns
ns
ns
ns
SDIDEM to SCKDSD set-up
time
SCKDSD to SDIDEM hold time
LATI2S pulse width low
tDHO
tCSL
tCSH
tCSS
tCSSU
tCSSH
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
LATI2S pulse width high
LATI2S rising to SCKDSD rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
