WM8728
Product Preview
MPU 2-WIRE INTERFACE TIMING
tSCF
tSCY
SCKDSD
tSSU tSHD
tSCH
tDHD tDSU
tDR
tESU
tSCL
tSCR
SDIDEM
tDF
Figure 6 Program Register Input Timing - 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCKDSD pulse cycle time
tSCY
tSCL
tSCH
tSSU
80
20
20
10
ns
ns
ns
ns
SCKDSD pulse width low
SCKDSD pulse width high
SDIDEM to SCKDSD data set-
up time for start signal
SDIDEM from SCKDSD data
hold time for start signal
tSHD
tDSU
tDHD
10
20
20
ns
ns
ns
SDIDEM to SCKDSD data set-
up time
SCKDSD to SDIDEM data hold
time
SCKDSD rise time
SCKDSD fall time
SDIDEM rise time
SDIDEM fall time
tSCR
tSCF
tDR
5
5
ns
ns
ns
ns
ns
5
tDF
5
SDIDEM to SCKDSD data set-
up time for stop signal
tESU
10
Notes:
1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.
2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.
3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire
mode.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
10
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
