WM8728
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DSD AUDIO MONOPHASE INTERFACE
tBCH
tBCL
MCLK
tBCY
DIN/LRCIN
tDS
tDH
Figure 3 Normal DSD timing requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
MCLK cycle time
tBCY
tBCH
tBCL
tDS
344
ns
ns
ns
ns
MCLK pulse width high
MCLK pulse width low
160
160
10
DIN/LRCIN set-up time to
MCLK rising edge
DIN/LRCIN hold time from
MCLK rising edge
tDH
10
ns
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
7