WM8728
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DSD AUDIO BIPHASE INTERFACE
tPH
tBCY
BCKIN
tBCH
tBCL
tMCL
tMCH
MCLK
tMCY
tSU
tHD
D0
D1
D1
D2
D2
DIN/LRCIN
Figure 4 Biphase DSD Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
tMCY
tMCH
tMCL
tPH
162.8
81.4
ns
ns
ns
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
MCLK cycle time
80
80
81.4
325.5
162.8
162.8
MCLK pulse width high
MCLK pulse width low
160
160
Phase shift between BCKIN
and MCLK
20
Data setup time to BCKIN
falling edge
tSU
tHD
10
10
ns
ns
Data hold time to BCKIN
rising edge
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
