WM8728
Production Data
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n
1
2
n
1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 10 DSP Late Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used
to operate the digital filters and the noise shaping circuits.
The WM8728 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase
differences or jitter on this clock. See Table 1
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCIN)
32kHz
4.096
5.6448
6.114
6.144
8.467
9.216
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
44.1kHz
48kHz
96kHz
192kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate
PD Rev 4.2 April 2004
15
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
