WM8728
Production Data
MPU 2-WIRE INTERFACE TIMING
Figure 5 Program Register Input Timing - 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCK pulse cycle time
tSCY
tSCL
tSCH
tSSU
80
20
20
10
ns
ns
ns
ns
SCK pulse width low
SCK pulse width high
SDIDEM to SCK data set-up
time for start signal
SDIDEM from SCK data hold
time for start signal
tSHD
tDSU
10
20
ns
ns
SDIDEM to SCK data set-up
time
SCK to SDIDEM data hold time
SCK rise time
tDHD
tSCR
tSCF
tDR
20
5
ns
ns
ns
ns
ns
ns
SCK fall time
5
SDIDEM rise time
SDIDEM fall time
5
tDF
5
SDIDEM to SCK data set-up
time for stop signal
tESU
10
Notes:
1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.
2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.
3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire
mode.
PD Rev 4.2 April 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
