WM8728
Production Data
REGISTER MAP
WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.
Using either 2-wire or 3-wire serial control mode as shown in Figure 13 and Figure 14.
B15
B14
B13
B12
B11
B10
B9
0
B8
B7
B6
LAT6
RAT6
0
B5
LAT5
RAT5
IW2
B4
B3
LAT3
RAT3
IW0
0
B2
LAT2
RAT2
B1
LAT1
RAT1
B0
LAT0
RAT0
M0
M1
M2
M3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
UPDATEL LAT7
UPDATER RAT7
LAT4
RAT4
IW1
0
1
0
0
0
0
0
PWDN DEEMPH MUT
I2S
0
1
IZD
0
BCP
REV
ATC
LRP
ADDRESS
DATA
Table 7 Mapping of Program Registers
REGISTER
ADDRESS
(A3,A2,A1,A0)
0000
BITS
NAME
DEFAULT
DESCRIPTION
[7:0]
8
LAT[7:0] 11111111 (0dB) Attenuation data for left channel in 0.5dB steps, see Table 10
DACL
UPDATEL
0
Attenuation data load control for left channel.
Attenuation
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on both channels.
0001
[7:0]
8
RAT[7:0] 11111111 (0dB) Attenuation data for right channel in 0.5dB steps, see Table 10
DACR
Attenuation
UPDATER
0
0
0
0
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on both channels.
Left and right DACs soft mute control.
0: No mute
0010
0
1
2
MUT
DAC Control
1: Mute
DEEMPH
PWDN
De-emphasis control.
0: De-emphasis off
1: De-emphasis on
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Audio data format select, see Table 15
Audio data format select, see Table 15
Polarity select for LRCIN/DSP mode select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
Attenuator Control.
[5:3]
0
IW[2:0]
I2S
0
0
0
0011
Interface
Control
1
LRP
2
ATC
0
0: All DACs use attenuation as programmed.
1: Right channel DACs use corresponding left DAC
attenuation
4
5
REV
BCP
0
0
Output phase reverse.
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
8
IZD
0
Infinite ZERO detection circuit control and automute control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
Table 8 Register Bit Descriptions
PD Rev 4.2 April 2004
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
