WM8716
Production Data
REGISTER
BITS
NAME
AL[7:0]
LDL
DEFAULT
DESCRIPTION
0
[7:0]
FF
0
Attenuation data for left channel.
Attenuation data load control for left channel.
Attenuation data for right channel.
Attenuation data load control for right channel.
Left and right DACs soft mute control.
De-emphasis control.
8
[7:0]
8
1
2
AR[7:0]
LDR
FF
0
0
MUT
DEM
OPE
0
1
0
2
0
Left and right DACs operation control.
Input audio data bit select.
Audio data format select.
[4:3]
0
IW[1:0]
I2S
0
3
0
1
LRP
0
Polarity of LRCIN select.
2
ATC
0
Attenuator control.
3
SR0
0
Digital filter slow roll-off select.
Output phase reverse.
4
REV
0
5
CKO
SF[1:0]
IZD
0
CLKO frequency select.
[7:6]
8
0
Sampling rate select.
0
Infinite zero detection circuit control.
Differential output mode.
4
[5:4]
6
DIFF
CDD
0
0
Clock loss detector disable.
Table 6 Register Bit Descriptions
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255
- ∞dB (mute),
X = 0
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 4.
X[7:0]
00(hex)
01(hex)
:
ATTENUATION LEVEL
- ∞dB (mute)
-127.0dB
:
:
:
FD(hex)
FE(hex)
FF(hex)
-1.0dB
-0.5dB
0.0dB
Table 7 Attenuation Control Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the
attenuation data for each register is applied separately to left and right channels.
w
PD Rev 4.1 September 2006
14
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
