WM8591
Product Preview
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R18 (12h)
0011000
3:0
ATK[3:0]
0010
(33.6ms/
1ms)
ALC/Limiter Attack (gain ramp-down) Time
ALC Mode:
Limiter Mode:
ALC Control 3
0000: 8.4ms
0000: 250us
0001: 500us…
0010: 1ms
0001: 16.8ms
0010: 33.6ms…
(time doubles with every step)
1010 or higher: 8.6s
(time doubles with every step)
1010 or higher: 256ms
7:4
DCY[3:0]
1001
ALC/Limiter Decay (gain ramp up) Time
(17.15s/
614.4ms)
ALC Mode:
Limiter Mode:
0000: 33.5ms
0001: 67.2ms
0000: 1.2ms
0001: 2.4ms
0010: 134.4ms ….(time
doubles for every step)
0010: 4.8ms ….(time doubles
for every step)
1001: 17.15s
1001: 614.4ms
1010 or higher: 34.3s
1010 or higher: 1.2288s
R20 (14h)
0010100
3:0
MAXATTEN
[3:0]
0110
Maximum Attenuation of PGA (Limiter only)
Limiter (attenuation below static)
(-6dB)
Limiter
Control
0000 to 0011
0100
-3dB
-4dB
….
(-1dB steps)
-14dB
1110
1111
-15dB
R21 (15h)
0010101
0
1
MUTERA
MUTELA
LRBOTH
RESET
0
Mute for Right Channel ADC:
0: Mute off
ADC Mux
Control
1: Mute on
0
0
Mute for Left Channel ADC:
0: Mute off
1: Mute on
8
Right Channel Input PGA Controlled by Left Channel Register:
0: Right channel uses RAG and MUTERA
1: Right channel uses LAG and MUTELA
R23 (17h)
0010111
[8:0]
Not reset
Writing any value to this register will apply a reset to the device
registers.
Software
Reset
R28 (1Ch)
0011100
0
ADCSYNCEN
BCLK_RATE
0
Enable the ADC Synchronizer:
0: Disabled
ADC/DAC
1: Enabled
Synchronization
3:2
00
Set ADCBCLK and DACBCLK output rate in Master Mode:
00: BCLK = MCLK/4 (MCLK in DSP Mode)
01: BCLK = MCLK/4 (MCLK in DSP Mode)
10: BCLK = 64fs
11: BCLK = 128fs
4
5
ADCMCLK2DAC
ADCMCLKX2
0
0
Set both ADC and DAC to use ADCMCLK:
0: DAC uses DACMCLK
1: DAC uses ADCMCLK
Allows DAC synchronizer to synchronize to ADC operating at 2x
DAC rate:
0: Disabled
1: Enabled
PP Rev 1.0 May 2005
42
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
