WM8591
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
3
ADCBCP
0
ADC BITCLK Polarity:
0: Normal – ADCLRC sampled on rising edge of
ADCBCLK; DOUT changes on falling edge of ADCBCLK
1: Inverted - ADCLRC sampled on falling edge of
ADCBCLK; DOUT changes on rising edge of ADCBCLK
5:4
ADCWL[1:0]
10
ADC Input Word Length:
00: 16-bit mode
01: 20-bit mode
10: 24-bit mode
11: 32-bit mode (not supported in right justified mode)
6
7
ADCMCLKINV
DACSYNCEN
ADCHPD
0
0
ADCMCLK Polarity:
0: non-inverted
1: inverted
Enable the DAC Synchronizer:
0: Disabled
1: Enabled
8
0
ADC High Pass Filter Powerdown:
0: HP Filter Enabled
1: HP Filter Disabled
R12 (0Ch)
0001100
2:0
ADCRATE[2:0]
010
Master Mode ADCMCLK:ADCLRC Ratio Select:
010: 256fs
Master Mode
Control
011: 384fs
100: 512fs
101: 768fs
3
ADCOSR
0
ADC Oversample Rate Select:
0: 128x oversampling
1: 64x oversampling
6:4
DACRATE[2:0]
010
Master Mode DACMCLK:DACLRC Ratio Select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
7
8
0
DACMS
ADCMS
PDWN
0
1
0
DAC Master/Slave Interface Mode Select:
0: Slave Mode – DACLRC and DACBCLK are inputs
1: Master Mode –DACLRC and DACBCLK are outputs
ADC Master/Slave Interface Mode Select:
0: Slave Mode – ADCLRC and ADCBCLK are inputs
1: Master Mode – ADCLRC and ADCBCLK are outputs
R13 (0Dh)
0001101
Chip Powerdown Control (works in tandem with ADCPD and
DACPD):
0: All circuits running, outputs are active
1: All circuits in power save mode, outputs muted
ADC Powerdown:
PWR Down
Control
1
2
ADCPD
DACPD
0
0
0: ADC enabled
1: ADC disabled
DAC Powerdown:
0: DAC enabled
1: DAC disabled
PP Rev 1.0 May 2005
40
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
