WM8591
Product Preview
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3 (03h)
0000011
7:0
LDA[7:0]
11111111
(0dB)
Digital Attenuation Data for Left Channel DACL in 0.5dB Steps
Digital
Attenuation
DACL
8
7:0
8
UPDATED
RDA[6:0]
UPDATED
MDA[7:0]
UPDATED
PHASE
Not latched
Controls Simultaneous Update of all Attenuation Latches:
0: Store LDA1 in intermediate latch (no change to output)
1: Store LDA1 and update attenuation on all channels
R4 (04h)
0000100
11111111
(0dB)
Digital Attenuation Data for Right Channel DACR in 0.5dB Steps
Digital
Attenuation
DACR
Not latched
Controls Simultaneous Update of all Attenuation Latches:
0: Store RDA1 in intermediate latch (no change to output)
1: Store RDA1 and update attenuation on all channels
R5 (05h)
0000101
7:0
8
11111111
(0dB)
Digital Attenuation Data for all DAC Channels in 0.5dB Steps
Master
Digital
Attenuation
Not latched
Controls Simultaneous Update of all Attenuation Latches:
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels
(All Channels)
R6 (06h)
0000110
1:0
0
00
0
Controls Phase of DAC Outputs (LEFT, RIGHT Channel):
0: Sets non inverted output phase
Phase Swaps
1: inverts phase of DAC output
R7 (07h)
0000111
DZCEN
DAC Digital Volume Zero Cross Enable:
0: Zero Cross detect disabled
DAC Control
1: Zero Cross detect enabled
ATC
IZD
0
0
Attenuator Control:
1
2
0: All DACs use attenuations as programmed
1: Right DAC uses left DAC attenuations
Infinite Zero Detection Circuit Control and Automute Control:
0: Infinite zero detect automute disabled
1: Infinite zero detect automute enabled
DAC and ADC Analogue Zero Cross Detect Timeout Disable:
0 : Timeout enabled
3
TOD
0
1: Timeout disabled
7:4
PL[3:0]
1001
DAC Output Control
PL[3:0]
Left
Right
PL[3:0]
Left
Right
Output
Output
Output
Output
0000
0001
0010
0011
0100
0101
0110
0111
Mute
Left
Mute
Mute
Mute
Mute
Left
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Right
Right
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Right
(L+R)/2
Left
Right
(L+R)/2
Left
PP Rev 1.0 May 2005
38
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
