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WM8591
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes. The ADC volume and mute also applies to the bypass signal path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R14 (0Eh)
0001110
Attenuation
ADCL
7:0
LAG[7:0]
11001111
(0dB)
Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See
Table 12.
8
ZCLA
0
Left Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
R15 (0Fh)
0001111
7:0
8
RAG[7:0]
ZCRA
11001111
(0dB)
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 12.
Attenuation
ADCR
0
0
0
0
Right Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
R21 (15h)
0010101
0
1
8
MUTERA
MUTELA
LRBOTH
Mute for Right Channel ADC
0: Mute Off
ADC Input Mux
1: Mute on
Mute for Left Channel ADC
0: Mute Off
1: Mute on
Right Channel Input PGA Controlled by Left Channel Register
0: Right channel uses RAG and MUTERA
1: Right channel uses LAG and MUTELA
PP Rev 1.0 May 2005
31
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
