WM8591
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ADC/DAC SYNCHRONIZATION
The WM8591 has a range of features which can be configured to enhance the performance of the
ADC and DAC when operated simultaneously.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11 (0Bh)
6
ADCMCLKINV
0
ADCMCLK Polarity:
0: non-inverted
1: inverted
ADC Interface
Control
7
0
4
5
DACSYNCEN
ADCSYNCEN
ADCMCLK2DAC
ADCMCLKX2
0
0
0
0
Enable the DAC Synchronizer:
0: Disabled
1: Enabled
R28 (1Ch)
0011100
Enable the ADC Synchronizer:
0: Disabled
ADC/DAC
1: Enabled
Synchronization
Set both ADC and DAC to use ADCMCLK:
0: DAC uses DACMCLK
1: DAC uses ADCMCLK
Allows DAC synchronizer to synchronize to ADC operating at
2x DAC rate:
0: Disabled
1: Enabled
6
7
DACMCLKINV
DACMCLKX2
0
0
DACMCLK Polarity:
0: non-inverted
1: inverted
Allows ADC synchronizer to synchronize to DAC operating at
2x ADC rate:
0: Disabled
1: Enabled
8
DACMCLK2ADC
0
Set both DAC and ADC to use DACMCLK:
0: ADC uses ADCMCLK
1: ADC uses DACMCLK
PP Rev 1.0 May 2005
32
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
