WM8591
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ADC GAIN CONTROL
The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the
analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right.
The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows
further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 12 shows how the
register maps the analogue and digital gains.
LAG/RAG[7:0]
ATTENUATION
LEVEL (AT
OUTPUT)
ANALOGUE PGA
DIGITAL
ATTENUATION
00(hex)
01(hex)
:
-∞ dB (mute)
-103dB
-21dB
-21dB
:
Digital mute
-82dB
:
:
-21.5dB
-21dB
:
A4(hex)
A5(hex)
:
-21dB
-21dB
:
-0.5dB
0dB
:
CF(hex)
:
0dB
0dB
0dB
:
:
:
FE(hex)
FF(hex)
+23.5dB
+24dB
+23.5dB
+24dB
0dB
0dB
Table 12 Analogue and Digital Gain Mapping for ADC
In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a
write, the gain will update only when the input signal approaches zero (midrail). This minimises
audible clicks and ‘zipper’ noise as the gain values change.
A timeout clock is also provided which will generate an update after a minimum of 131072 master
clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting
TOD.
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
3
TOD
0
Analogue PGA Zero Cross Detect
Timeout Disable
0000111
0 : Timeout enabled
1: Timeout disabled
Timeout Clock Disable
PP Rev 1.0 May 2005
30
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
