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WM8591
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8591 can be configured using the Control Interface. All unused bits should be set to ‘0’.
REGISTER
B
B
B
B
B
B
B
9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
(HEX)
0FF
15 14 13 12 11 10
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
UPDATED
LDA[7:0]
UPDATED
RDA[7:0]
MDA[7:0]
0FF
UPDATED
0FF
0
0
0
0
0
0
0
0
0
PHASE[1:0]
000
PL[3:0]
TOD
IZD
ATC
DZCEN
090
ZFLAG
POL
004
R9 (09h)
0
0
0
1
0
0
1
0
0
0
0
0
DMUTE
DZFM [1:0]
DEEMPH
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (Odh)
R14 (0Eh)
R15 (0Fh)
R16 (10h)
R17 (11h)
R18 (12h)
R20 (14h)
R21 (15h)
R23 (17h)
R28 (1Ch)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
DACOSR
ADCHPD
ADCMS
0
DACWL[1:0]
ADCWL[1:0]
DACBCP DACLRP
ADCBCP ADCLRP
ADCOSR
DACFMT[1:0]
ADCFMT[1:0]
ADCRATE[2:0]
PDWN
022
022
DACSYNCEN ADCMCLKINV
DACMS
0
DACRATE[2:0]
122
0
0
0
0
DACPD ADCPD
000
ZCLA
LAG[7:0]
RAG[7:0]
0CF
0CF
1FE
180
ZCRA
LCSEL[1:0]
MAXGAIN[2:0]
0
LCT[3:0]
LCMODE
ALCZC
0
0
0
0
0
0
0
0
0
DCY[3:0]
ATK[3:0]
MAXATTEN[3:0]
MUTELA MUTERA
092
0
0
0
0
0
0
0
0
006
LRBOTH
0
000
SOFTWARE RESET
not reset
000
DACMCLK2ADCDACMCLKX2DACMCLKINV ADCMCLKX2 ADCMCLK2DAC
BCLK_RATE
0
ADCSYNCEN
PP Rev 1.0 May 2005
37
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
