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WM8591
ATTACK AND DECAY TIMES
The limiter and ALC have different attack and decay times which determine their operation. However,
the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and
ATK control the decay and attack times, respectively.
Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the
PGA gain to ramp up across 90% of its range (e.g. from –21dB up to +20 dB). When in limiter mode,
it is defined as the time it takes for the gain to ramp up by 6dB.
The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from
33.6ms, 67.2ms, 134.4ms etc. to 34.41s. For the limiter this gives times from 1.2ms, 2.4ms etc., up
to 1.2288s.
Attack time (Gain Ramp-Down) When in ALC mode, this is defined as the time that it takes for the
PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in
limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB.
The attack time can be programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to
8.6s for the ALC and from 250us, 500us, etc. up to 256ms.
The time it takes for the recording level to return to its target value or static gain value therefore
depends on both the attack/decay time and on the gain adjustment required. If the gain adjustment is
small, it will be shorter than the attack/decay time.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R18 (12h)
0010010
ALC
3:0
ATK[3:0]
0010
LC Attack (Gain Ramp-down) Time
ALC mode
Limiter Mode
0000: 250us
0001: 500us…
0010: 1ms
0000: 8.4ms
Control 3
0001: 16.8ms
0010: 33.6ms…
(time doubles with
every step)
(time doubles with
every step)
1010 or higher:
8.6s
1010 or higher: 256ms
7:4
DCY [3:0]
1001
LC Decay (Gain Ramp-up) Time
ALC mode
Limiter mode
0000: 33.5ms
0001: 67.2ms
0010: 134.4ms
0000: 1.2ms
0001: 2.4ms
0010: 4.8ms ….(time
….(time doubles for doubles for every
every step)
step)
1001: 17.15s
1001: 614.4ms
1010 or higher:
34.3s
1010 or higher:
1.2288s
ZERO CROSS
The PGA has a zero cross detector to prevent gain changes introducing noise to the signal. In ALC
mode the register bit ALCZC allows this to be turned off if desired.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R17 (11h)
0010001
7
ALCZC
1
PGA Zero Cross Enable:
0 : disabled
(enabled)
ALC Control 2
1: enabled
PP Rev 1.0 May 2005
35
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
