WM8591
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input
signal
PGA
gain
signal
after
ALC
ALC
target
level
hold decay
time time
attack
time
Figure 22 ALC Operation
The gain control circuit is enabled by setting the LCMODE control bit. The user can select between
Limiter mode and three different ALC modes using the LCSEL control bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R17 (11h)
0010001
8
LCMODE
1
ALC/Limiter Select
0 = ALC Mode
ALC Control 2
R16 (10h)
1 = Limiter Mode
LC Function Select
00 = Disabled
8:7
LCSEL
11
0010000
ALC Control 1
01 = Right channel only
10 = Left channel only
11 = Stereo
Both the ALC and Limiter functions can operate in stereo or single channel modes. In stereo mode,
the ALC/Limiter operates on both PGAs. In single channel mode, only one PGA is controlled by the
ALC/Limiter mechanism, while the other channel runs independently with its PGA gain set through
the control register.
When enabled, the threshold for the limiter or target level for the ALC is programmed using the LCT
control bits. This allows the threshold/target level to be programmed between -1dB and -16dB in 1dB
steps. Note that for the ALC, target levels of -1dB and -2dB give a threshold of -3dB. This is
because the ALC can give erroneous operation if the target level is set too high.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16 (10h)
0010000
3:0
LCT[3:0]
1110
Limiter Threshold/ALC Target Level in
1.5dB Steps:
(-1.5dB)
0000: -22.5dB FS
0001: -21dB FS
…
ALC Control 1
1101: -3dB FS
1110: -1.5dB FS
1111: 0dB FS
PP Rev 1.0 May 2005
34
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
